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conv_bias_int8.cpp 48 kB

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  1. /**
  2. * \file dnn/test/cuda/conv_bias_int8.cpp
  3. * MegEngine is Licensed under the Apache License, Version 2.0 (the "License")
  4. *
  5. * Copyright (c) 2014-2021 Megvii Inc. All rights reserved.
  6. *
  7. * Unless required by applicable law or agreed to in writing,
  8. * software distributed under the License is distributed on an
  9. * "AS IS" BASIS, WITHOUT ARRANTIES OR CONDITIONS OF ANY KIND, either express or
  10. * implied.
  11. */
  12. #include "megdnn/oprs/nn.h"
  13. #include "src/common/utils.h"
  14. #include "src/cuda/cudnn_with_check.h"
  15. #include "test/common/checker.h"
  16. #include "test/common/conv_bias.h"
  17. #include "test/cuda/benchmark.h"
  18. #include "test/cuda/fixture.h"
  19. #include "test/cuda/utils.h"
  20. #include "test/common/tensor.h"
  21. #include "test/common/workspace_wrapper.h"
  22. #include "test/cuda/conv_test_utils.h"
  23. namespace megdnn {
  24. namespace test {
  25. namespace conv{
  26. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_CUDNN_CONVOLUTION) {
  27. require_compute_capability(7, 5);
  28. conv_bias::check_conv_bias(
  29. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  30. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  31. handle_cuda(), "DEFAULT:CUDNN:ConvBiasActivation:",
  32. param::ConvBias::Format::NCHW4);
  33. }
  34. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_1x1) {
  35. require_compute_capability(6, 1);
  36. conv_bias::check_conv_bias(
  37. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  38. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  39. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  40. param::ConvBias::Format::NCHW4, conv_bias::get_int8_nchw4_args(1));
  41. }
  42. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_3x3) {
  43. require_compute_capability(6, 1);
  44. conv_bias::check_conv_bias(
  45. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  46. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  47. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  48. param::ConvBias::Format::NCHW4);
  49. }
  50. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_5x5) {
  51. require_compute_capability(6, 1);
  52. conv_bias::check_conv_bias(
  53. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  54. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  55. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  56. param::ConvBias::Format::NCHW4, conv_bias::get_int8_nchw4_args(5));
  57. }
  58. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_7x7) {
  59. require_compute_capability(6, 1);
  60. conv_bias::check_conv_bias(
  61. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  62. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  63. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  64. param::ConvBias::Format::NCHW4, conv_bias::get_int8_nchw4_args(7));
  65. }
  66. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_WITH_Z) {
  67. require_compute_capability(6, 1);
  68. Checker<ConvBiasForward> checker(handle_cuda());
  69. checker.set_before_exec_callback(
  70. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  71. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM"));
  72. UniformIntRNG rng{-3, 3};
  73. UniformIntRNG bias_rng{-50, 50};
  74. checker.set_rng(0, &rng)
  75. .set_rng(1, &rng)
  76. .set_rng(2, &bias_rng)
  77. .set_rng(3, &rng)
  78. .set_dtype(0, dtype::QuantizedS8{1.2f})
  79. .set_dtype(1, dtype::QuantizedS8{1.3f})
  80. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  81. .set_dtype(3, dtype::QuantizedS8{1.1f})
  82. .set_dtype(4, dtype::QuantizedS8{1.0f})
  83. .set_epsilon(1 + 1e-3)
  84. .set_max_avg_error(1e-1)
  85. .set_max_avg_biased_error(1e-1);
  86. param::ConvBias param;
  87. param.pad_h = param.pad_w = 1;
  88. param.stride_h = param.stride_w = 1;
  89. param.format = param::ConvBias::Format::NCHW4;
  90. checker.set_param(param).execs({{32, 4, 12, 12, 4},
  91. {16, 4, 3, 3, 4},
  92. {1, 4, 1, 1, 4},
  93. {32, 4, 12, 12, 4},
  94. {}});
  95. }
  96. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_STRIDE2_WITH_Z) {
  97. require_compute_capability(6, 1);
  98. Checker<ConvBiasForward> checker(handle_cuda());
  99. checker.set_before_exec_callback(
  100. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  101. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM"));
  102. UniformIntRNG rng{-3, 3};
  103. UniformIntRNG bias_rng{-50, 50};
  104. checker.set_rng(0, &rng)
  105. .set_rng(1, &rng)
  106. .set_rng(2, &bias_rng)
  107. .set_rng(3, &rng)
  108. .set_dtype(0, dtype::QuantizedS8{1.2f})
  109. .set_dtype(1, dtype::QuantizedS8{1.3f})
  110. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  111. .set_dtype(3, dtype::QuantizedS8{1.1f})
  112. .set_dtype(4, dtype::QuantizedS8{1.0f})
  113. .set_epsilon(1 + 1e-3)
  114. .set_max_avg_error(1e-1)
  115. .set_max_avg_biased_error(1e-1);
  116. param::ConvBias param;
  117. param.pad_h = param.pad_w = 1;
  118. param.stride_h = param.stride_w = 2;
  119. param.format = param::ConvBias::Format::NCHW4;
  120. checker.set_param(param).execs({{32, 4, 12, 12, 4},
  121. {16, 4, 3, 3, 4},
  122. {1, 4, 1, 1, 4},
  123. {32, 4, 6, 6, 4},
  124. {}});
  125. }
  126. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_CHECK_BOUNDS_1x1) {
  127. require_compute_capability(6, 1);
  128. conv_bias::check_conv_bias(
  129. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  130. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  131. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  132. param::ConvBias::Format::NCHW4,
  133. conv_bias::get_int8_nchw4_args_check_bounds(1));
  134. }
  135. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_CHECK_BOUNDS_3x3) {
  136. require_compute_capability(6, 1);
  137. conv_bias::check_conv_bias(
  138. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  139. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  140. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  141. param::ConvBias::Format::NCHW4,
  142. conv_bias::get_int8_nchw4_args_check_bounds(3));
  143. }
  144. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_CHECK_BOUNDS_5x5) {
  145. require_compute_capability(6, 1);
  146. conv_bias::check_conv_bias(
  147. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  148. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  149. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  150. param::ConvBias::Format::NCHW4,
  151. conv_bias::get_int8_nchw4_args_check_bounds(5));
  152. }
  153. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_CHECK_BOUNDS_7x7) {
  154. require_compute_capability(6, 1);
  155. conv_bias::check_conv_bias(
  156. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  157. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  158. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  159. param::ConvBias::Format::NCHW4,
  160. conv_bias::get_int8_nchw4_args_check_bounds(7));
  161. }
  162. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4) {
  163. require_compute_capability(6, 1);
  164. conv_bias::check_conv_bias(
  165. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  166. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  167. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  168. param::ConvBias::Format::CHWN4);
  169. }
  170. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_WITH_Z) {
  171. require_compute_capability(6, 1);
  172. Checker<ConvBiasForward> checker(handle_cuda());
  173. checker.set_before_exec_callback(
  174. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  175. "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM"));
  176. UniformIntRNG rng{-3, 3};
  177. UniformIntRNG bias_rng{-50, 50};
  178. checker.set_rng(0, &rng)
  179. .set_rng(1, &rng)
  180. .set_rng(2, &bias_rng)
  181. .set_rng(3, &rng)
  182. .set_dtype(0, dtype::QuantizedS8{1.2f})
  183. .set_dtype(1, dtype::QuantizedS8{1.3f})
  184. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  185. .set_dtype(3, dtype::QuantizedS8{1.1f})
  186. .set_dtype(4, dtype::QuantizedS8{1.1f})
  187. .set_epsilon(1 + 1e-3)
  188. .set_max_avg_error(1e-1)
  189. .set_max_avg_biased_error(1e-1);
  190. param::ConvBias param;
  191. param.pad_h = param.pad_w = 1;
  192. param.stride_h = param.stride_w = 1;
  193. param.format = param::ConvBias::Format::CHWN4;
  194. checker.set_param(param).execs({{4, 12, 12, 32, 4},
  195. {4, 3, 3, 16, 4},
  196. {4, 1, 1, 1, 4},
  197. {4, 12, 12, 32, 4},
  198. {}});
  199. }
  200. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_HSWISH) {
  201. require_compute_capability(6, 1);
  202. Checker<ConvBiasForward> checker(handle_cuda());
  203. checker.set_before_exec_callback(
  204. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  205. "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM"));
  206. UniformIntRNG rng{-3, 3};
  207. UniformIntRNG bias_rng{-50, 50};
  208. checker.set_rng(0, &rng)
  209. .set_rng(1, &rng)
  210. .set_rng(2, &bias_rng)
  211. .set_rng(3, &rng)
  212. .set_dtype(0, dtype::QuantizedS8{1.2f})
  213. .set_dtype(1, dtype::QuantizedS8{1.3f})
  214. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  215. .set_dtype(4, dtype::QuantizedS8{0.001f})
  216. .set_epsilon(1 + 1e-3)
  217. .set_max_avg_error(1e-1)
  218. .set_max_avg_biased_error(1e-1);
  219. param::ConvBias param;
  220. param.pad_h = param.pad_w = 1;
  221. param.stride_h = param.stride_w = 1;
  222. param.format = param::ConvBias::Format::CHWN4;
  223. param.nonlineMode = param::ConvBias::NonlineMode::H_SWISH;
  224. checker.set_param(param).execs(
  225. {{4, 12, 12, 32, 4}, {4, 3, 3, 16, 4}, {4, 1, 1, 1, 4}, {}, {}});
  226. }
  227. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_CHECK_BOUNDS) {
  228. require_compute_capability(6, 1);
  229. conv_bias::check_conv_bias(
  230. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  231. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  232. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  233. param::ConvBias::Format::CHWN4,
  234. conv_bias::get_int8_chwn4_args_check_bounds(3));
  235. }
  236. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_1x1) {
  237. require_compute_capability(6, 1);
  238. conv_bias::check_conv_bias(
  239. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  240. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  241. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  242. param::ConvBias::Format::CHWN4,
  243. conv_bias::get_int8_chwn4_small_channel_args(1));
  244. }
  245. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_3x3) {
  246. require_compute_capability(6, 1);
  247. conv_bias::check_conv_bias(
  248. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  249. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  250. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  251. param::ConvBias::Format::CHWN4,
  252. conv_bias::get_int8_chwn4_small_channel_args(3));
  253. }
  254. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_5x5) {
  255. require_compute_capability(6, 1);
  256. conv_bias::check_conv_bias(
  257. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  258. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  259. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  260. param::ConvBias::Format::CHWN4,
  261. conv_bias::get_int8_chwn4_small_channel_args(5));
  262. }
  263. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_7x7) {
  264. require_compute_capability(6, 1);
  265. conv_bias::check_conv_bias(
  266. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  267. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  268. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  269. param::ConvBias::Format::CHWN4,
  270. conv_bias::get_int8_chwn4_small_channel_args(7));
  271. }
  272. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_SMALL_CHANNEL_CHECK_BOUNDS) {
  273. require_compute_capability(6, 1);
  274. conv_bias::check_conv_bias(
  275. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  276. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  277. handle_cuda(), "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  278. param::ConvBias::Format::NCHW4,
  279. conv_bias::get_int8_nchw4_small_channel_args_check_bounds(3));
  280. }
  281. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_1x1_CHECK_BOUNDS) {
  282. require_compute_capability(6, 1);
  283. conv_bias::check_conv_bias(
  284. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  285. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  286. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  287. param::ConvBias::Format::CHWN4,
  288. conv_bias::get_int8_chwn4_small_channel_args_check_bounds(1));
  289. }
  290. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_5x5_CHECK_BOUNDS) {
  291. require_compute_capability(6, 1);
  292. conv_bias::check_conv_bias(
  293. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  294. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  295. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  296. param::ConvBias::Format::CHWN4,
  297. conv_bias::get_int8_chwn4_small_channel_args_check_bounds(5));
  298. }
  299. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL_7x7_CHECK_BOUNDS) {
  300. require_compute_capability(6, 1);
  301. conv_bias::check_conv_bias(
  302. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  303. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  304. handle_cuda(), "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  305. param::ConvBias::Format::CHWN4,
  306. conv_bias::get_int8_chwn4_small_channel_args_check_bounds(7));
  307. }
  308. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_1x1) {
  309. require_compute_capability(7, 5);
  310. conv_bias::check_conv_bias(
  311. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  312. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  313. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  314. param::ConvBias::Format::NCHW4,
  315. conv_bias::get_int8_nchw4_tensorcore_args(1));
  316. }
  317. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_3x3) {
  318. require_compute_capability(7, 5);
  319. conv_bias::check_conv_bias(
  320. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  321. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  322. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  323. param::ConvBias::Format::NCHW4,
  324. conv_bias::get_int8_nchw4_tensorcore_args(3));
  325. }
  326. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_5x5) {
  327. require_compute_capability(7, 5);
  328. conv_bias::check_conv_bias(
  329. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  330. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  331. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  332. param::ConvBias::Format::NCHW4,
  333. conv_bias::get_int8_nchw4_tensorcore_args(5));
  334. }
  335. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_7x7) {
  336. require_compute_capability(7, 5);
  337. conv_bias::check_conv_bias(
  338. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  339. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  340. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  341. param::ConvBias::Format::NCHW4,
  342. conv_bias::get_int8_nchw4_tensorcore_args(7));
  343. }
  344. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_CHECK_BOUNDS_ALGO_0) {
  345. require_compute_capability(7, 5);
  346. conv_bias::check_conv_bias(
  347. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  348. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  349. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  350. param::ConvBias::Format::NCHW4,
  351. conv_bias::get_int8_nchw4_args_check_bounds(3));
  352. }
  353. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_CHECK_BOUNDS_ALGO_1) {
  354. require_compute_capability(7, 5);
  355. conv_bias::check_conv_bias(
  356. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  357. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  358. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma8x32x16",
  359. param::ConvBias::Format::NCHW4,
  360. conv_bias::get_int8_nchw4_args_check_bounds(3));
  361. }
  362. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_CHECK_BOUNDS_ALGO_2) {
  363. require_compute_capability(7, 5);
  364. conv_bias::check_conv_bias(
  365. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  366. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  367. handle_cuda(), "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma32x8x16",
  368. param::ConvBias::Format::NCHW4,
  369. conv_bias::get_int8_nchw4_args_check_bounds(3));
  370. }
  371. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_ALGO_0) {
  372. require_compute_capability(7, 5);
  373. conv_bias::check_conv_bias(
  374. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  375. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  376. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  377. param::ConvBias::Format::CHWN4,
  378. conv_bias::get_int8_chwn4_tensorcore_args(3));
  379. }
  380. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_ALGO_1) {
  381. require_compute_capability(7, 5);
  382. conv_bias::check_conv_bias(
  383. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  384. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  385. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma32x8x16",
  386. param::ConvBias::Format::CHWN4,
  387. conv_bias::get_int8_chwn4_tensorcore_args(3));
  388. }
  389. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_ALGO_2) {
  390. require_compute_capability(7, 5);
  391. conv_bias::check_conv_bias(
  392. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  393. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  394. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma8x32x16",
  395. param::ConvBias::Format::CHWN4,
  396. conv_bias::get_int8_chwn4_tensorcore_args(3));
  397. }
  398. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_CHECK_BOUNDS_1x1) {
  399. require_compute_capability(7, 5);
  400. conv_bias::check_conv_bias(
  401. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  402. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  403. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  404. param::ConvBias::Format::CHWN4,
  405. conv_bias::get_int8_chwn4_args_check_bounds(1));
  406. }
  407. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_CHECK_BOUNDS_5x5) {
  408. require_compute_capability(7, 5);
  409. conv_bias::check_conv_bias(
  410. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  411. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  412. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  413. param::ConvBias::Format::CHWN4,
  414. conv_bias::get_int8_chwn4_args_check_bounds(5));
  415. }
  416. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_CHECK_BOUNDS_7x7) {
  417. require_compute_capability(7, 5);
  418. conv_bias::check_conv_bias(
  419. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  420. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  421. handle_cuda(), "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  422. param::ConvBias::Format::CHWN4,
  423. conv_bias::get_int8_chwn4_args_check_bounds(7));
  424. }
  425. TEST_F(CUDA, CONV_BIAS_INT8_NCHW4_TENSORCORE_WITH_Z) {
  426. require_compute_capability(7, 5);
  427. Checker<ConvBiasForward> checker(handle_cuda());
  428. checker.set_before_exec_callback(
  429. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  430. "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16"));
  431. UniformIntRNG rng{-3, 3};
  432. UniformIntRNG bias_rng{-50, 50};
  433. checker.set_rng(0, &rng)
  434. .set_rng(1, &rng)
  435. .set_rng(2, &bias_rng)
  436. .set_rng(3, &rng)
  437. .set_dtype(0, dtype::QuantizedS8{1.2f})
  438. .set_dtype(1, dtype::QuantizedS8{1.3f})
  439. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  440. .set_dtype(3, dtype::QuantizedS8{1.1f})
  441. .set_dtype(4, dtype::QuantizedS8{1.0f})
  442. .set_epsilon(1 + 1e-3)
  443. .set_max_avg_error(1e-1)
  444. .set_max_avg_biased_error(1e-1);
  445. param::ConvBias param;
  446. param.pad_h = param.pad_w = 1;
  447. param.stride_h = param.stride_w = 1;
  448. param.format = param::ConvBias::Format::NCHW4;
  449. checker.set_param(param).execs({{64, 8, 12, 12, 4},
  450. {64, 8, 3, 3, 4},
  451. {1, 16, 1, 1, 4},
  452. {64, 16, 12, 12, 4},
  453. {}});
  454. }
  455. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_TENSORCORE_WITH_Z) {
  456. require_compute_capability(7, 5);
  457. Checker<ConvBiasForward> checker(handle_cuda());
  458. checker.set_before_exec_callback(
  459. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  460. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16"));
  461. UniformIntRNG rng{-3, 3};
  462. UniformIntRNG bias_rng{-50, 50};
  463. checker.set_rng(0, &rng)
  464. .set_rng(1, &rng)
  465. .set_rng(2, &bias_rng)
  466. .set_rng(3, &rng)
  467. .set_dtype(0, dtype::QuantizedS8{1.2f})
  468. .set_dtype(1, dtype::QuantizedS8{1.3f})
  469. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  470. .set_dtype(3, dtype::QuantizedS8{1.1f})
  471. .set_dtype(4, dtype::QuantizedS8{1.0f})
  472. .set_epsilon(1 + 1e-3)
  473. .set_max_avg_error(1e-1)
  474. .set_max_avg_biased_error(1e-1);
  475. param::ConvBias param;
  476. param.pad_h = param.pad_w = 1;
  477. param.stride_h = param.stride_w = 1;
  478. param.format = param::ConvBias::Format::CHWN4;
  479. checker.set_param(param).execs({{8, 12, 12, 64, 4},
  480. {8, 3, 3, 64, 4},
  481. {16, 1, 1, 1, 4},
  482. {16, 12, 12, 64, 4},
  483. {}});
  484. }
  485. TEST_F(CUDA,
  486. CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_CHECK_BOUNDS_ALGO_0) {
  487. require_compute_capability(7, 5);
  488. conv_bias::check_conv_bias(
  489. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  490. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  491. handle_cuda(),
  492. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma16x16x16",
  493. param::ConvBias::Format::CHWN4,
  494. conv_bias::get_int8_chwn4_args_check_bounds(3));
  495. }
  496. TEST_F(CUDA,
  497. CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_CHECK_BOUNDS_ALGO_1) {
  498. require_compute_capability(7, 5);
  499. conv_bias::check_conv_bias(
  500. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  501. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  502. handle_cuda(),
  503. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma8x32x16",
  504. param::ConvBias::Format::CHWN4,
  505. conv_bias::get_int8_chwn4_args_check_bounds(3));
  506. }
  507. TEST_F(CUDA,
  508. CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_CHECK_BOUNDS_ALGO_2) {
  509. require_compute_capability(7, 5);
  510. conv_bias::check_conv_bias(
  511. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  512. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  513. handle_cuda(),
  514. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma32x8x16",
  515. param::ConvBias::Format::CHWN4,
  516. conv_bias::get_int8_chwn4_args_check_bounds(3));
  517. }
  518. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_ALGO_0) {
  519. require_compute_capability(7, 5);
  520. conv_bias::check_conv_bias(
  521. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  522. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  523. handle_cuda(),
  524. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma16x16x16",
  525. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  526. }
  527. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_ALGO_1) {
  528. require_compute_capability(7, 5);
  529. conv_bias::check_conv_bias(
  530. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  531. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  532. handle_cuda(),
  533. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma8x32x16",
  534. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  535. }
  536. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_REFORMAT_FILTER_TENSORCORE_ALGO_2) {
  537. require_compute_capability(7, 5);
  538. conv_bias::check_conv_bias(
  539. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  540. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  541. handle_cuda(),
  542. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_REORDER_FILTER_mma32x8x16",
  543. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  544. }
  545. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_ALGO_0) {
  546. require_compute_capability(7, 5);
  547. conv_bias::check_conv_bias(
  548. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  549. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  550. handle_cuda(),
  551. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma16x16x16",
  552. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  553. }
  554. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_ALGO_1) {
  555. require_compute_capability(7, 5);
  556. conv_bias::check_conv_bias(
  557. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  558. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  559. handle_cuda(),
  560. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma8x32x16",
  561. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  562. }
  563. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_ALGO_2) {
  564. require_compute_capability(7, 5);
  565. conv_bias::check_conv_bias(
  566. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  567. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.3f},
  568. handle_cuda(),
  569. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma32x8x16",
  570. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(3));
  571. }
  572. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_1x1) {
  573. require_compute_capability(7, 5);
  574. conv_bias::check_conv_bias(
  575. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  576. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  577. handle_cuda(),
  578. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma16x16x16",
  579. param::ConvBias::Format::CHWN4, conv_bias::get_int8_chwn4_args(1));
  580. }
  581. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_5x5) {
  582. require_compute_capability(7, 5);
  583. conv_bias::check_conv_bias(
  584. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  585. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  586. handle_cuda(),
  587. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma16x16x16",
  588. param::ConvBias::Format::CHWN4,
  589. conv_bias::get_int8_chwn4_args_small_batch(5));
  590. }
  591. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_7x7) {
  592. require_compute_capability(7, 5);
  593. conv_bias::check_conv_bias(
  594. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  595. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  596. handle_cuda(),
  597. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma16x16x16",
  598. param::ConvBias::Format::CHWN4,
  599. conv_bias::get_int8_chwn4_args_small_batch(7));
  600. }
  601. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_5x5_ALGO_1) {
  602. require_compute_capability(7, 5);
  603. conv_bias::check_conv_bias(
  604. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  605. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  606. handle_cuda(),
  607. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma32x8x16",
  608. param::ConvBias::Format::CHWN4,
  609. conv_bias::get_int8_chwn4_args_small_batch(5));
  610. }
  611. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_5x5_ALGO_2) {
  612. require_compute_capability(7, 5);
  613. conv_bias::check_conv_bias(
  614. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  615. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  616. handle_cuda(),
  617. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma8x32x16",
  618. param::ConvBias::Format::CHWN4,
  619. conv_bias::get_int8_chwn4_args_small_batch(5));
  620. }
  621. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_1x1_ALGO_1) {
  622. require_compute_capability(7, 5);
  623. conv_bias::check_conv_bias(
  624. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  625. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  626. handle_cuda(),
  627. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma32x8x16",
  628. param::ConvBias::Format::CHWN4,
  629. conv_bias::get_int8_chwn4_args_small_batch(1));
  630. }
  631. TEST_F(CUDA, CONV_BIAS_INT8_CHWN4_UNROLL_WIDTH_TENSORCORE_1x1_ALGO_2) {
  632. require_compute_capability(7, 5);
  633. conv_bias::check_conv_bias(
  634. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  635. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.1f},
  636. handle_cuda(),
  637. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_UNROLL_WIDTH_mma8x32x16",
  638. param::ConvBias::Format::CHWN4,
  639. conv_bias::get_int8_chwn4_args_small_batch(1));
  640. }
  641. TEST_F(CUDA, FALLBACK_CONV_QS8) {
  642. require_compute_capability_eq(7, 5);
  643. Checker<ConvBiasForward> checker(handle_cuda());
  644. auto check = [&checker](const std::string&& algo) {
  645. checker.set_before_exec_callback(
  646. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(algo.c_str()));
  647. UniformIntRNG rng{-3, 3};
  648. UniformIntRNG bias_rng{-50, 50};
  649. checker.set_rng(0, &rng)
  650. .set_rng(1, &rng)
  651. .set_rng(2, &bias_rng)
  652. .set_rng(3, &rng)
  653. .set_dtype(0, dtype::QuantizedS8{1.2f})
  654. .set_dtype(1, dtype::QuantizedS8{1.3f})
  655. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  656. .set_dtype(3, dtype::QuantizedS8{19.990229f})
  657. .set_dtype(4, dtype::QuantizedS8{19.990228f})
  658. .set_epsilon(1e-3)
  659. .set_max_avg_error(1e-1)
  660. .set_max_avg_biased_error(1e-3);
  661. param::ConvBias param;
  662. param.pad_h = param.pad_w = 1;
  663. param.stride_h = param.stride_w = 2;
  664. param.format = param::ConvBias::Format::NCHW;
  665. checker.set_param(param).execs({{16, 15, 14, 14},
  666. {28, 15, 3, 3},
  667. {1, 28, 1, 1},
  668. {16, 28, 7, 7},
  669. {}});
  670. checker.set_param(param).execs({{16, 32, 14, 14},
  671. {32, 32, 3, 3},
  672. {1, 32, 1, 1},
  673. {},
  674. {}});
  675. };
  676. check("FALLBACK_CONV_NCHW_QS8");
  677. }
  678. TEST_F(CUDA, FALLBACK_CONV_QS8_F32) {
  679. require_compute_capability_eq(7, 5);
  680. Checker<ConvBiasForward> checker(handle_cuda());
  681. auto check = [&checker](const std::string&& algo) {
  682. checker.set_before_exec_callback(
  683. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(algo.c_str()));
  684. UniformIntRNG rng{-3, 3};
  685. UniformFloatRNG bias_rng{-50.f, 50.f};
  686. checker.set_rng(0, &rng)
  687. .set_rng(1, &rng)
  688. .set_rng(2, &bias_rng)
  689. .set_rng(3, &rng)
  690. .set_dtype(0, dtype::QuantizedS8{1.2f})
  691. .set_dtype(1, dtype::QuantizedS8{1.3f})
  692. .set_dtype(2, dtype::Float32{})
  693. .set_dtype(3, dtype::Float32{})
  694. .set_dtype(4, dtype::Float32{})
  695. .set_epsilon(1e-3)
  696. .set_max_avg_error(1e-1)
  697. .set_max_avg_biased_error(1e-3);
  698. param::ConvBias param;
  699. param.pad_h = param.pad_w = 1;
  700. param.stride_h = param.stride_w = 2;
  701. param.format = param::ConvBias::Format::NCHW;
  702. checker.set_param(param).execs({{16, 15, 14, 14},
  703. {28, 15, 3, 3},
  704. {1, 28, 1, 1},
  705. {16, 28, 7, 7},
  706. {}});
  707. checker.set_param(param).execs({{16, 32, 14, 14},
  708. {32, 32, 3, 3},
  709. {1, 32, 1, 1},
  710. {},
  711. {}});
  712. };
  713. check("FALLBACK_CONV_NCHW_QS8");
  714. }
  715. TEST_F(CUDA, CUTLASS_CONV_BIAS_INT8_WEIGHT_PREPROCESS) {
  716. require_compute_capability(6, 1);
  717. Checker<ConvBiasForward, OprWeightPreprocessProxy<ConvBiasForward>> checker(
  718. handle_cuda());
  719. auto check = [&checker](const std::string& algo) {
  720. checker.set_before_exec_callback(
  721. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(algo.c_str()));
  722. UniformIntRNG rng{-16, 16};
  723. UniformIntRNG bias_rng{-50, 50};
  724. UniformIntRNG const_rng{1, 1};
  725. checker.set_rng(0, &rng)
  726. .set_rng(1, &rng)
  727. .set_rng(2, &bias_rng)
  728. .set_rng(3, &rng)
  729. .set_dtype(0, dtype::QuantizedS8{1.2f})
  730. .set_dtype(1, dtype::QuantizedS8{1.3f})
  731. .set_dtype(2, dtype::QuantizedS32{1.2f * 1.3f})
  732. .set_dtype(3, dtype::QuantizedS8{1.3f})
  733. .set_dtype(4, dtype::QuantizedS8{1.0f})
  734. .set_epsilon(1 + 1e-3)
  735. .set_max_avg_error(1e-1)
  736. .set_max_avg_biased_error(1e-3);
  737. param::ConvBias param;
  738. param.pad_h = param.pad_w = 1;
  739. param.stride_h = param.stride_w = 2;
  740. param.format = param::ConvBias::Format::NCHW4;
  741. checker.set_param(param).execs({{16, 4, 14, 14, 4},
  742. {16, 4, 3, 3, 4},
  743. {1, 4, 1, 1, 4},
  744. {},
  745. {}});
  746. };
  747. check("INT8_NCHW4_DOTPROD_IMPLICIT_GEMM_128X32X32_64X32X32");
  748. check("INT8_NCHW4_DOTPROD_IMPLICIT_GEMM_16X64X8_16X64X8");
  749. }
  750. #if CUDA_VERSION >= 10020
  751. /// \note: we only check several cases and block sizes in megdnn_test, the
  752. /// full testcases are written in cutlass repository
  753. TEST_F(CUDA, CUTLASS_CONV_BIAS_INT8_NCHW32_IMMA) {
  754. require_compute_capability_eq(7, 5);
  755. Checker<ConvBiasForward> checker(handle_cuda());
  756. auto check = [&checker](const std::string& algo) {
  757. checker.set_before_exec_callback(
  758. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(algo.c_str()));
  759. UniformIntRNG rng{-8, 8};
  760. UniformIntRNG bias_rng{-50, 50};
  761. UniformIntRNG const_rng{1, 1};
  762. // use scale that are all integers to avoid rouding error
  763. checker.set_rng(0, &rng)
  764. .set_rng(1, &rng)
  765. .set_rng(2, &bias_rng)
  766. .set_rng(3, &rng)
  767. .set_dtype(0, dtype::QuantizedS8{6.0f})
  768. .set_dtype(1, dtype::QuantizedS8{1.0f})
  769. .set_dtype(2, dtype::QuantizedS32{6.0f})
  770. .set_dtype(3, dtype::QuantizedS8{1.0f})
  771. .set_dtype(4, dtype::QuantizedS8{6.0f})
  772. .set_epsilon(1e-3);
  773. param::ConvBias param;
  774. param.pad_h = param.pad_w = 1;
  775. param.stride_h = param.stride_w = 1;
  776. param.format = param::ConvBias::Format::NCHW32;
  777. checker.set_param(param).execs({{16, 16, 7, 7, 32},
  778. {512, 16, 3, 3, 32},
  779. {1, 16, 1, 1, 32},
  780. {},
  781. {}});
  782. param.nonlineMode = param::ConvBias::NonlineMode::RELU;
  783. checker.set_param(param).execs({{16, 16, 7, 7, 32},
  784. {512, 16, 1, 1, 32},
  785. {1, 16, 1, 1, 32},
  786. {},
  787. {}});
  788. param.nonlineMode = param::ConvBias::NonlineMode::H_SWISH;
  789. checker.set_param(param).execs({{16, 16, 7, 7, 32},
  790. {512, 16, 3, 3, 32},
  791. {1, 16, 1, 1, 32},
  792. {},
  793. {}});
  794. // use non integer scale
  795. param.nonlineMode = param::ConvBias::NonlineMode::H_SWISH;
  796. checker.set_dtype(0, dtype::QuantizedS8{1.1f})
  797. .set_dtype(1, dtype::QuantizedS8{1.2f})
  798. .set_dtype(2, dtype::QuantizedS32{1.1f * 1.2f})
  799. .set_dtype(3, dtype::QuantizedS8{1.1f})
  800. .set_dtype(4, dtype::QuantizedS8{6.0f})
  801. .set_epsilon(1 + 1e-3)
  802. .set_max_avg_error(1e-1)
  803. .set_max_avg_biased_error(1e-1)
  804. .execs({{16, 16, 7, 7, 32},
  805. {512, 16, 3, 3, 32},
  806. {1, 16, 1, 1, 32},
  807. {16, 16, 7, 7, 32},
  808. {}});
  809. };
  810. std::string algo = ConvBias::algo_name<ConvBias::DirectParam>(
  811. "INT8_NCHW32_IMMA_IMPLICIT_GEMM_256X128X64_64X64X64",
  812. ConvBias::DirectParam{});
  813. check(algo);
  814. algo = ConvBias::algo_name<ConvBias::DirectParam>(
  815. "INT8_NCHW32_IMMA_IMPLICIT_GEMM_32X64X64_32X16X64",
  816. ConvBias::DirectParam{});
  817. check(algo);
  818. }
  819. #endif
  820. TEST_F(CUDA, CUTLASS_CONV_BIAS_INT8_NCHW4_NCHW) {
  821. require_compute_capability(6, 1);
  822. using namespace conv_bias;
  823. Checker<ConvBiasForward> checker(handle_cuda());
  824. UniformIntRNG int_rng{-3, 3};
  825. UniformFloatRNG float_rng{-50, 50};
  826. ConvBias::Param param;
  827. param.format = ConvBias::Param::Format::NCHW4_NCHW;
  828. param.nonlineMode = ConvBias::Param::NonlineMode::IDENTITY;
  829. checker.set_before_exec_callback(
  830. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  831. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM"));
  832. checker.set_dtype(0, dtype::QuantizedS8(1.9980618f))
  833. .set_dtype(1, dtype::QuantizedS8(1.9980927f))
  834. .set_dtype(2, dtype::Float32())
  835. .set_dtype(3, dtype::Float32())
  836. .set_dtype(4, dtype::Float32())
  837. .set_rng(0, &int_rng)
  838. .set_rng(1, &int_rng)
  839. .set_rng(2, &float_rng)
  840. .set_rng(3, &float_rng)
  841. .set_param(param);
  842. auto opr = handle_cuda()->create_operator<ConvBias>();
  843. auto run = [&](const TensorShapeArray& shapes) {
  844. opr->param() = param;
  845. TensorLayout dst_layout;
  846. opr->deduce_layout({shapes[0], dtype::Float32()},
  847. {shapes[1], dtype::Float32()}, {}, {}, dst_layout);
  848. checker.execs({shapes[0], shapes[1], shapes[2], dst_layout, {}});
  849. };
  850. run({{16, 4, 23, 40, 4}, {20, 4, 3, 3, 4}, {1, 20, 1, 1}});
  851. run({{16, 4, 92, 160, 4}, {24, 4, 3, 3, 4}, {1, 24, 1, 1}});
  852. run({{16, 4, 92, 160, 4}, {20, 4, 3, 3, 4}, {1, 20, 1, 1}});
  853. run({{16, 4, 92, 160, 4}, {16, 4, 3, 3, 4}, {1, 16, 1, 1}});
  854. run({{16, 4, 92, 160, 4}, {8, 4, 3, 3, 4}, {1, 8, 1, 1}});
  855. run({{16, 4, 46, 80, 4}, {4, 4, 3, 3, 4}, {1, 4, 1, 1}});
  856. }
  857. TEST_F(CUDA, CUTLASS_CONV_BIAS_INT8_NCHW4_NCHW32) {
  858. require_compute_capability(6, 1);
  859. using namespace conv_bias;
  860. Checker<ConvBiasForward> checker(handle_cuda());
  861. UniformIntRNG int_rng{-3, 3};
  862. UniformIntRNG bias_rng{-50, 50};
  863. ConvBias::Param param;
  864. param.format = ConvBias::Param::Format::NCHW4_NCHW32;
  865. param.nonlineMode = ConvBias::Param::NonlineMode::IDENTITY;
  866. checker.set_before_exec_callback(
  867. conv_bias::ConvBiasAlgoChecker<ConvBiasForward>(
  868. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM"));
  869. checker.set_dtype(0, dtype::QuantizedS8(1.9980618f))
  870. .set_dtype(1, dtype::QuantizedS8(1.9980927f))
  871. .set_dtype(2, dtype::QuantizedS32(1.9980618f * 1.9980927f))
  872. .set_dtype(3, dtype::QuantizedS8(1.9980618f))
  873. .set_dtype(4, dtype::QuantizedS8(1.9980618f))
  874. .set_rng(0, &int_rng)
  875. .set_rng(1, &int_rng)
  876. .set_rng(2, &bias_rng)
  877. .set_rng(3, &int_rng)
  878. .set_param(param);
  879. auto run = [&](const TensorShapeArray& shapes) {
  880. checker.execs({shapes[0], shapes[1], shapes[2], {}, {}});
  881. };
  882. run({{16, 4, 23, 40, 4}, {32, 4, 3, 3, 4}, {1, 1, 1, 1, 32}});
  883. run({{16, 4, 92, 160, 4}, {32, 4, 3, 3, 4}, {1, 1, 1, 1, 32}});
  884. run({{16, 4, 46, 80, 4}, {32, 4, 3, 3, 4}, {1, 1, 1, 1, 32}});
  885. }
  886. #if CUDA_VERSION >= 10020
  887. TEST_F(CUDA, CUTLASS_CONV_BIAS_INT8_NCHW32_NCHW4) {
  888. require_compute_capability(7, 5);
  889. using namespace conv_bias;
  890. Checker<ConvBiasForward> checker(handle_cuda());
  891. UniformIntRNG int_rng{-3, 3};
  892. UniformIntRNG bias_rng{-50, 50};
  893. ConvBias::Param param;
  894. param.format = ConvBias::Param::Format::NCHW32_NCHW4;
  895. param.nonlineMode = ConvBias::Param::NonlineMode::IDENTITY;
  896. checker.set_before_exec_callback(conv_bias::ConvBiasAlgoChecker<
  897. ConvBiasForward>(
  898. ConvBias::algo_name<ConvBias::DirectParam>(
  899. "INT8_NCHW32_IMMA_IMPLICIT_GEMM_256X128X64_64X64X64",
  900. ConvBias::DirectParam{})
  901. .c_str()));
  902. checker.set_dtype(0, dtype::QuantizedS8(1.9980618f))
  903. .set_dtype(1, dtype::QuantizedS8(1.9980927f))
  904. .set_dtype(2, dtype::QuantizedS32(1.9980618f * 1.9980927f))
  905. .set_dtype(3, dtype::QuantizedS8(1.9980618f))
  906. .set_dtype(4, dtype::QuantizedS8(1.9980618f))
  907. .set_rng(0, &int_rng)
  908. .set_rng(1, &int_rng)
  909. .set_rng(2, &bias_rng)
  910. .set_rng(3, &int_rng)
  911. .set_param(param);
  912. auto run = [&](const TensorShapeArray& shapes) {
  913. checker.execs({shapes[0], shapes[1], shapes[2], {}, {}});
  914. };
  915. run({{16, 2, 23, 40, 32}, {20, 2, 3, 3, 32}, {1, 5, 1, 1, 4}});
  916. run({{16, 1, 92, 160, 32}, {24, 1, 3, 3, 32}, {1, 6, 1, 1, 4}});
  917. run({{16, 2, 46, 80, 32}, {4, 2, 3, 3, 32}, {1, 1, 1, 1, 4}});
  918. }
  919. #endif
  920. #if MEGDNN_WITH_BENCHMARK
  921. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_CHWN4) {
  922. require_compute_capability(6, 1);
  923. benchmark_target_algo(
  924. handle_cuda(), get_resnet50_bench_args(), dtype::QuantizedS8{1.2f},
  925. dtype::QuantizedS8{1.3f}, dtype::QuantizedS32{1.2f * 1.3f},
  926. dtype::QuantizedS8{1.0f}, "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  927. param::ConvBias::Format::CHWN4);
  928. }
  929. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_NCHW4) {
  930. require_compute_capability(6, 1);
  931. benchmark_target_algo(
  932. handle_cuda(), get_resnet50_bench_args(), dtype::QuantizedS8{1.2f},
  933. dtype::QuantizedS8{1.3f}, dtype::QuantizedS32{1.2f * 1.3f},
  934. dtype::QuantizedS8{1.0f}, "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM",
  935. param::ConvBias::Format::NCHW4);
  936. }
  937. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_CHWN4_TENSORCORE) {
  938. require_compute_capability(7, 5);
  939. benchmark_target_algo_with_cudnn_tsc(
  940. handle_cuda(), get_resnet50_bench_args(256),
  941. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  942. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f},
  943. "INT8_CHWN4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  944. param::ConvBias::Format::CHWN4);
  945. }
  946. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_CHWN4_TENSORCORE_ALL_ALGO) {
  947. require_compute_capability(7, 5);
  948. benchmark_target_algo_with_cudnn_tsc(
  949. handle_cuda(), get_resnet50_bench_args(256),
  950. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  951. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f}, nullptr,
  952. param::ConvBias::Format::CHWN4);
  953. }
  954. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_CHWN4_DET_ALL_ALGO) {
  955. require_compute_capability(7, 5);
  956. benchmark_target_algo_with_cudnn_tsc(
  957. handle_cuda(), get_detection_bench_args(), dtype::QuantizedS8{1.2f},
  958. dtype::QuantizedS8{1.3f}, dtype::QuantizedS32{1.2f * 1.3f},
  959. dtype::QuantizedS8{1.0f}, nullptr, param::ConvBias::Format::CHWN4);
  960. }
  961. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_NCHW4_TENSORCORE) {
  962. require_compute_capability(7, 5);
  963. benchmark_target_algo_with_cudnn_tsc(
  964. handle_cuda(), get_resnet50_bench_args(256),
  965. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  966. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f},
  967. "INT8_NCHW4_IMMA_IMPLICIT_GEMM_mma16x16x16",
  968. param::ConvBias::Format::NCHW4);
  969. }
  970. TEST_F(CUDA, BENCHMARK_CONV_BIAS_INT8_CHWN4_SMALL_CHANNEL) {
  971. require_compute_capability(6, 1);
  972. std::vector<BenchArgs> args;
  973. args.push_back(BenchArgs{64, 4, 224, 224, 64, 7, 2});
  974. benchmark_target_algo(
  975. handle_cuda(), args, dtype::QuantizedS8{1.2f},
  976. dtype::QuantizedS8{1.3f}, dtype::QuantizedS32{1.2f * 1.3f},
  977. dtype::QuantizedS8{1.0f}, "INT8_CHWN4_DOTPROD_IMPLICIT_GEMM",
  978. param::ConvBias::Format::CHWN4);
  979. }
  980. #if CUDA_VERSION >= 10020
  981. TEST_F(CUDA, BENCHMARK_CUTLASS_CONV_BIAS_INT8_NCHW32) {
  982. require_compute_capability(7, 5);
  983. benchmark_target_algo_with_cudnn_tsc(
  984. handle_cuda(), get_resnet50_bench_args(256),
  985. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  986. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f},
  987. "DIRECT:INT8_NCHW32_IMMA_IMPLICIT_GEMM",
  988. param::ConvBias::Format::NCHW32);
  989. }
  990. #endif
  991. TEST_F(CUDA, BENCHMARK_CUTLASS_CONV_BIAS_INT8_NCHW4) {
  992. require_compute_capability(6, 1);
  993. benchmark_target_algo(
  994. handle_cuda(), get_resnet50_bench_args(64),
  995. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  996. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f},
  997. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM", param::ConvBias::Format::NCHW4);
  998. }
  999. TEST_F(CUDA, BENCHMARK_SASS_CONV_BIAS_INT8_NCHW4_DET_FIRST) {
  1000. require_compute_capability(6, 1);
  1001. std::string algo = ConvBias::algo_name<ConvBias::DirectParam>(
  1002. "SASS_INT8_NCHW4_DOTPROD_IMPLICIT_GEMM_128X32_64",
  1003. ConvBias::DirectParam{});
  1004. benchmark_target_algo(handle_cuda(), get_det_first_bench_args(16),
  1005. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  1006. dtype::QuantizedS32{1.2f * 1.3f},
  1007. dtype::QuantizedS8{1.0f}, algo.c_str(),
  1008. param::ConvBias::Format::NCHW4);
  1009. }
  1010. TEST_F(CUDA, BENCHMARK_CUTLASS_CONV_BIAS_INT8_NCHW4_DET_FIRST) {
  1011. require_compute_capability(6, 1);
  1012. benchmark_target_algo(
  1013. handle_cuda(), get_det_first_bench_args(16),
  1014. dtype::QuantizedS8{1.2f}, dtype::QuantizedS8{1.3f},
  1015. dtype::QuantizedS32{1.2f * 1.3f}, dtype::QuantizedS8{1.0f},
  1016. "INT8_NCHW4_DOTPROD_IMPLICIT_GEMM_16", param::ConvBias::Format::NCHW4);
  1017. }
  1018. #endif
  1019. }
  1020. } // namespace test
  1021. } // namespace megdnn
  1022. // vim: syntax=cpp.doxygen

MegEngine 安装包中集成了使用 GPU 运行代码所需的 CUDA 环境,不用区分 CPU 和 GPU 版。 如果想要运行 GPU 程序,请确保机器本身配有 GPU 硬件设备并安装好驱动。 如果你想体验在云端 GPU 算力平台进行深度学习开发的感觉,欢迎访问 MegStudio 平台