From 6aade1336d0a278a98bf20b74f757c29ea76f4e4 Mon Sep 17 00:00:00 2001 From: Megvii Engine Team Date: Fri, 21 Aug 2020 10:15:34 +0800 Subject: [PATCH] fix(dnn/fallback): disable im2col/conv1x1/conv1x1_gemv Quantized8Asymm in x86 GitOrigin-RevId: b094634254141364ab11a493adca28f90d5d57b2 --- dnn/src/fallback/conv_bias/conv1x1/algos.cpp | 20 +++++++------------- .../conv_bias/conv1x1/algos_conv1x1_gemv.cpp | 8 ++++++++ dnn/src/fallback/conv_bias/im2col/algos.cpp | 8 ++++++++ 3 files changed, 23 insertions(+), 13 deletions(-) diff --git a/dnn/src/fallback/conv_bias/conv1x1/algos.cpp b/dnn/src/fallback/conv_bias/conv1x1/algos.cpp index e64d168d..8dea1707 100644 --- a/dnn/src/fallback/conv_bias/conv1x1/algos.cpp +++ b/dnn/src/fallback/conv_bias/conv1x1/algos.cpp @@ -204,18 +204,6 @@ ConvBiasImpl::AlgoConv1x1::dispatch_preprocess_kerns( bool ConvBiasImpl::AlgoConv1x1::usable(const NCBKernSizeParam& param, AlgoSelectionStrategy) const { MIDOUT_BEGIN(megdnn_fallback_conv1x1, 0, 2) { - //! x86 only support nchw -#if MEGDNN_X86 - if (param.filter_meta.format != param::ConvBias::Format::NCHW) { - return false; - } -#else - if (param.filter_meta.format != param::ConvBias::Format::NCHW && - param.filter_meta.format != param::ConvBias::Format::NCHW44 && - param.filter_meta.format != param::ConvBias::Format::NCHW44_DOT) { - return false; - } -#endif size_t FH = param.filter_meta.spatial[0], FW = param.filter_meta.spatial[1]; size_t PH = param.filter_meta.padding[0], @@ -239,7 +227,7 @@ bool ConvBiasImpl::AlgoConv1x1::usable(const NCBKernSizeParam& param, return false; } } -#else +#else //! x86 only support nchw mode if (format != param::ConvBias::Format::NCHW) { return false; } @@ -259,6 +247,12 @@ bool ConvBiasImpl::AlgoConv1x1::usable(const NCBKernSizeParam& param, param.src_type.enumv() != DTypeEnum::Float32)) { return false; } + //! x86 disable Quntized8Asymm +#if MEGDNN_X86 + if (param.src_type.enumv() == DTypeEnum::Quantized8Asymm) { + return false; + } +#endif //! make sure 8x8x16 and 8x8x32 biasmode is nobias and nonlineMode //! is identity otherwise return false mean that 8x8x32 and 8x8x16 //! not support PostProcess diff --git a/dnn/src/fallback/conv_bias/conv1x1/algos_conv1x1_gemv.cpp b/dnn/src/fallback/conv_bias/conv1x1/algos_conv1x1_gemv.cpp index 83a3f024..d76677ad 100644 --- a/dnn/src/fallback/conv_bias/conv1x1/algos_conv1x1_gemv.cpp +++ b/dnn/src/fallback/conv_bias/conv1x1/algos_conv1x1_gemv.cpp @@ -455,6 +455,14 @@ bool ConvBiasImpl::AlgoConv1x1Gemv::usable(const NCBKernSizeParam& param, param.src_type.enumv() != DTypeEnum::Float32)) { return false; } + + //! x86 disable Quntized8Asymm +#if MEGDNN_X86 + if (param.src_type.enumv() == DTypeEnum::Quantized8Asymm) { + return false; + } +#endif + if (format == param::ConvBias::Format::NCHW44) { if (param.src_type.enumv() != DTypeEnum::Float32 && param.src_type.enumv() != DTypeEnum::Int8 && diff --git a/dnn/src/fallback/conv_bias/im2col/algos.cpp b/dnn/src/fallback/conv_bias/im2col/algos.cpp index 7d5fafc9..bcb4bd18 100644 --- a/dnn/src/fallback/conv_bias/im2col/algos.cpp +++ b/dnn/src/fallback/conv_bias/im2col/algos.cpp @@ -377,6 +377,14 @@ bool ConvBiasImpl::AlgoIm2col::usable( param.src_type.enumv() != DTypeEnum::Float32)) { return false; } + + //! x86 disable Quntized8Asymm +#if MEGDNN_X86 + if (param.src_type.enumv() == DTypeEnum::Quantized8Asymm) { + return false; + } +#endif + //! make sure 8x8x16 and 8x8x32 biasmode is nobias and nonlineMode is //! identity otherwise return false mean that 8x8x32 and 8x8x16 not //! support PostProcess