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config.h 6.3 kB

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  1. /**
  2. * Copyright 2020 Huawei Technologies Co., Ltd
  3. * Licensed under the Apache License, Version 2.0 (the "License");
  4. * you may not use this file except in compliance with the License.
  5. * You may obtain a copy of the License at
  6. * http://www.apache.org/licenses/LICENSE-2.0
  7. * Unless required by applicable law or agreed to in writing, software
  8. * distributed under the License is distributed on an "AS IS" BASIS,
  9. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. * See the License for the specific language governing permissions and
  11. * limitations under the License.
  12. */
  13. #ifndef __CCE_RUNTIME_CONFIG_H__
  14. #define __CCE_RUNTIME_CONFIG_H__
  15. #include "base.h"
  16. #if defined(__cplusplus)
  17. extern "C" {
  18. #endif
  19. #define PLAT_COMBINE(arch, chip, ver) ((arch << 16) | (chip << 8) | (ver))
  20. #define PLAT_GET_ARCH(type) ((type >> 16) & 0xffff)
  21. #define PLAT_GET_CHIP(type) ((type >> 8) & 0xff)
  22. #define PLAT_GET_VER(type) (type & 0xff)
  23. typedef enum tagRtArchType {
  24. ARCH_BEGIN = 0,
  25. ARCH_V100 = ARCH_BEGIN,
  26. ARCH_V200,
  27. ARCH_END,
  28. } rtArchType_t;
  29. typedef enum tagRtChipType {
  30. CHIP_BEGIN = 0,
  31. CHIP_MINI = CHIP_BEGIN,
  32. CHIP_CLOUD,
  33. CHIP_MDC,
  34. CHIP_LHISI,
  35. CHIP_DC,
  36. CHIP_CLOUD_V2,
  37. CHIP_NO_DEVICE,
  38. CHIP_END,
  39. } rtChipType_t;
  40. typedef enum tagRtAicpuScheType {
  41. SCHEDULE_SOFTWARE = 0, /* Software Schedule */
  42. SCHEDULE_SOFTWARE_OPT,
  43. SCHEDULE_HARDWARE, /* HWTS Schedule */
  44. } rtAicpuScheType;
  45. typedef enum tagRtDeviceCapabilityType {
  46. RT_SCHEDULE_SOFTWARE = 0, // Software Schedule
  47. RT_SCHEDULE_SOFTWARE_OPT,
  48. RT_SCHEDULE_HARDWARE, // HWTS Schedule
  49. RT_AICPU_BLOCKING_OP_NOT_SUPPORT,
  50. RT_AICPU_BLOCKING_OP_SUPPORT, // 1910/1980/1951 ts support AICPU blocking operation
  51. } rtDeviceCapabilityType;
  52. typedef enum tagRtVersion {
  53. VER_BEGIN = 0,
  54. VER_NA = VER_BEGIN,
  55. VER_ES,
  56. VER_CS,
  57. VER_SD3403,
  58. VER_END,
  59. } rtVersion_t;
  60. /* match rtChipType_t */
  61. typedef enum tagRtPlatformType {
  62. PLATFORM_BEGIN = 0,
  63. PLATFORM_MINI_V1 = PLATFORM_BEGIN,
  64. PLATFORM_CLOUD_V1,
  65. PLATFORM_MINI_V2,
  66. PLATFORM_LHISI_ES,
  67. PLATFORM_LHISI_CS,
  68. PLATFORM_DC,
  69. PLATFORM_CLOUD_V2,
  70. PLATFORM_LHISI_SD3403,
  71. PLATFORM_END,
  72. } rtPlatformType_t;
  73. typedef enum tagRtCubeFracMKNFp16 {
  74. RT_CUBE_MKN_FP16_2_16_16 = 0,
  75. RT_CUBE_MKN_FP16_4_16_16,
  76. RT_CUBE_MKN_FP16_16_16_16,
  77. RT_CUBE_MKN_FP16_Default,
  78. } rtCubeFracMKNFp16_t;
  79. typedef enum tagRtCubeFracMKNInt8 {
  80. RT_CUBE_MKN_INT8_2_32_16 = 0,
  81. RT_CUBE_MKN_INT8_4_32_4,
  82. RT_CUBE_MKN_INT8_4_32_16,
  83. RT_CUBE_MKN_INT8_16_32_16,
  84. RT_CUBE_MKN_INT8_Default,
  85. } rtCubeFracMKNInt8_t;
  86. typedef enum tagRtVecFracVmulMKNFp16 {
  87. RT_VEC_VMUL_MKN_FP16_1_16_16 = 0,
  88. RT_VEC_VMUL_MKN_FP16_Default,
  89. } rtVecFracVmulMKNFp16_t;
  90. typedef enum tagRtVecFracVmulMKNInt8 {
  91. RT_VEC_VMUL_MKN_INT8_1_32_16 = 0,
  92. RT_VEC_VMUL_MKN_INT8_Default,
  93. } rtVecFracVmulMKNInt8_t;
  94. typedef struct tagRtAiCoreSpec {
  95. uint32_t cubeFreq;
  96. uint32_t cubeMSize;
  97. uint32_t cubeKSize;
  98. uint32_t cubeNSize;
  99. rtCubeFracMKNFp16_t cubeFracMKNFp16;
  100. rtCubeFracMKNInt8_t cubeFracMKNInt8;
  101. rtVecFracVmulMKNFp16_t vecFracVmulMKNFp16;
  102. rtVecFracVmulMKNInt8_t vecFracVmulMKNInt8;
  103. } rtAiCoreSpec_t;
  104. typedef struct tagRtAiCoreRatesPara {
  105. uint32_t ddrRate;
  106. uint32_t l2Rate;
  107. uint32_t l2ReadRate;
  108. uint32_t l2WriteRate;
  109. uint32_t l1ToL0ARate;
  110. uint32_t l1ToL0BRate;
  111. uint32_t l0CToUBRate;
  112. uint32_t ubToL2;
  113. uint32_t ubToDDR;
  114. uint32_t ubToL1;
  115. } rtAiCoreMemoryRates_t;
  116. typedef struct tagRtMemoryConfig {
  117. uint32_t flowtableSize;
  118. uint32_t compilerSize;
  119. } rtMemoryConfig_t;
  120. typedef struct tagRtPlatformConfig {
  121. uint32_t platformConfig;
  122. } rtPlatformConfig_t;
  123. typedef enum tagRTTaskTimeoutType {
  124. RT_TIMEOUT_TYPE_OP_WAIT = 0,
  125. RT_TIMEOUT_TYPE_OP_EXECUTE,
  126. } rtTaskTimeoutType_t;
  127. /**
  128. * @ingroup
  129. * @brief get AI core count
  130. * @param [in] aiCoreCnt
  131. * @return aiCoreCnt
  132. */
  133. RTS_API rtError_t rtGetAiCoreCount(uint32_t *aiCoreCnt);
  134. /**
  135. * @ingroup
  136. * @brief get AI cpu count
  137. * @param [in] aiCpuCnt
  138. * @return aiCpuCnt
  139. */
  140. RTS_API rtError_t rtGetAiCpuCount(uint32_t *aiCpuCnt);
  141. /**
  142. * @ingroup
  143. * @brief get AI core frequency
  144. * @param [in] aiCoreSpec
  145. * @return aiCoreSpec
  146. */
  147. RTS_API rtError_t rtGetAiCoreSpec(rtAiCoreSpec_t *aiCoreSpec);
  148. /**
  149. * @ingroup
  150. * @brief AI get core band Info
  151. * @param [in] aiCoreMemoryRates
  152. * @return aiCoreMemoryRates
  153. */
  154. RTS_API rtError_t rtGetAiCoreMemoryRates(rtAiCoreMemoryRates_t *aiCoreMemoryRates);
  155. /**
  156. * @ingroup
  157. * @brief AI get core buffer Info,FlowTable Size,Compiler Size
  158. * @param [in] memoryConfig
  159. * @return memoryConfig
  160. */
  161. RTS_API rtError_t rtGetMemoryConfig(rtMemoryConfig_t *memoryConfig);
  162. /**
  163. * @ingroup
  164. * @brief get l2 buffer Info,virtual baseaddr,Size
  165. * @param [in] stream
  166. * @return RT_ERROR_NONE for ok, errno for failed
  167. */
  168. RTS_API rtError_t rtMemGetL2Info(rtStream_t stream, void **ptr, uint32_t *size);
  169. /**
  170. * @ingroup
  171. * @brief get runtime version. The version is returned as (1000 major + 10 minor). For example, RUNTIME 9.2 would be
  172. * represented by 9020.
  173. * @param [out] runtimeVersion
  174. * @return RT_ERROR_NONE for ok
  175. * @return RT_ERROR_INVALID_VALUE for error input
  176. */
  177. RTS_API rtError_t rtGetRuntimeVersion(uint32_t *runtimeVersion);
  178. /**
  179. * @ingroup
  180. * @brief get device feature ability by device id, such as task schedule ability.
  181. * @param [in] deviceId
  182. * @param [in] moduleType
  183. * @param [in] featureType
  184. * @param [out] value
  185. * @return RT_ERROR_NONE for ok
  186. * @return RT_ERROR_INVALID_VALUE for error input
  187. */
  188. RTS_API rtError_t rtGetDeviceCapability(int32_t deviceId, int32_t moduleType, int32_t featureType, int32_t *value);
  189. /**
  190. * @ingroup
  191. * @brief set event wait task timeout time.
  192. * @param [in] timeout
  193. * @return RT_ERROR_NONE for ok
  194. * @return RT_ERROR_INVALID_VALUE for error input
  195. */
  196. RTS_API rtError_t rtSetOpWaitTimeOut(uint32_t timeout);
  197. /**
  198. * @ingroup
  199. * @brief set op execute task timeout time.
  200. * @param [in] timeout
  201. * @return RT_ERROR_NONE for ok
  202. * @return RT_ERROR_INVALID_VALUE for error input
  203. */
  204. RTS_API rtError_t rtSetOpExecuteTimeOut(uint32_t timeout);
  205. #if defined(__cplusplus)
  206. }
  207. #endif
  208. #endif // __CCE_RUNTIME_STREAM_H__

图引擎模块(GE)是MindSpore的一个子模块,其代码由C++实现,位于前端模块ME和底层硬件之间,起到承接作用。图引擎模块以ME下发的图作为输入,然后进行一系列的深度图优化操作,最后输出一张可以在底层硬件上高效运行的图。GE针对昇腾AI处理器的硬件结构特点,做了特定的优化工作,以此来充分发挥出昇腾AI处理器的强大算力。在进行模型训练/推理时,GE会被自动调用而用户并不感知。GE主要由GE API和GE Core两部分组成,详细的架构图如下所示