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config.h 4.6 kB

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  1. /**
  2. * Copyright 2020 Huawei Technologies Co., Ltd
  3. * Licensed under the Apache License, Version 2.0 (the "License");
  4. * you may not use this file except in compliance with the License.
  5. * You may obtain a copy of the License at
  6. * http://www.apache.org/licenses/LICENSE-2.0
  7. * Unless required by applicable law or agreed to in writing, software
  8. * distributed under the License is distributed on an "AS IS" BASIS,
  9. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. * See the License for the specific language governing permissions and
  11. * limitations under the License.
  12. */
  13. #ifndef __CCE_RUNTIME_CONFIG_H__
  14. #define __CCE_RUNTIME_CONFIG_H__
  15. #include "base.h"
  16. #if defined(__cplusplus) && !defined(COMPILE_OMG_PACKAGE)
  17. extern "C" {
  18. #endif
  19. #define PLAT_COMBINE(arch, chip, ver) ((arch << 16) | (chip << 8) | (ver))
  20. #define PLAT_GET_ARCH(type) ((type >> 16) & 0xffff)
  21. #define PLAT_GET_CHIP(type) ((type >> 8) & 0xff)
  22. #define PLAT_GET_VER(type) (type & 0xff)
  23. typedef enum tagRtArchType {
  24. ARCH_BEGIN = 0,
  25. ARCH_V100 = ARCH_BEGIN,
  26. ARCH_V200,
  27. ARCH_END,
  28. } rtArchType_t;
  29. typedef enum tagRtChipType {
  30. CHIP_BEGIN = 0,
  31. CHIP_MINI = CHIP_BEGIN,
  32. CHIP_CLOUD,
  33. CHIP_MDC,
  34. CHIP_LHISI,
  35. CHIP_DC,
  36. CHIP_END,
  37. } rtChipType_t;
  38. typedef enum tagRtVersion {
  39. VER_BEGIN = 0,
  40. VER_NA = VER_BEGIN,
  41. VER_ES,
  42. VER_CS,
  43. VER_END,
  44. } rtVersion_t;
  45. /* match rtChipType_t */
  46. typedef enum tagRtPlatformType {
  47. PLATFORM_BEGIN = 0,
  48. PLATFORM_MINI_V1 = PLATFORM_BEGIN,
  49. PLATFORM_CLOUD_V1,
  50. PLATFORM_MINI_V2,
  51. PLATFORM_LHISI_ES,
  52. PLATFORM_LHISI_CS,
  53. PLATFORM_DC,
  54. PLATFORM_END,
  55. } rtPlatformType_t;
  56. typedef enum tagRtCubeFracMKNFp16 {
  57. RT_CUBE_MKN_FP16_2_16_16 = 0,
  58. RT_CUBE_MKN_FP16_4_16_16,
  59. RT_CUBE_MKN_FP16_16_16_16,
  60. RT_CUBE_MKN_FP16_Default,
  61. } rtCubeFracMKNFp16_t;
  62. typedef enum tagRtCubeFracMKNInt8 {
  63. RT_CUBE_MKN_INT8_2_32_16 = 0,
  64. RT_CUBE_MKN_INT8_4_32_4,
  65. RT_CUBE_MKN_INT8_4_32_16,
  66. RT_CUBE_MKN_INT8_16_32_16,
  67. RT_CUBE_MKN_INT8_Default,
  68. } rtCubeFracMKNInt8_t;
  69. typedef enum tagRtVecFracVmulMKNFp16 {
  70. RT_VEC_VMUL_MKN_FP16_1_16_16 = 0,
  71. RT_VEC_VMUL_MKN_FP16_Default,
  72. } rtVecFracVmulMKNFp16_t;
  73. typedef enum tagRtVecFracVmulMKNInt8 {
  74. RT_VEC_VMUL_MKN_INT8_1_32_16 = 0,
  75. RT_VEC_VMUL_MKN_INT8_Default,
  76. } rtVecFracVmulMKNInt8_t;
  77. typedef struct tagRtAiCoreSpec {
  78. uint32_t cubeFreq;
  79. uint32_t cubeMSize;
  80. uint32_t cubeKSize;
  81. uint32_t cubeNSize;
  82. rtCubeFracMKNFp16_t cubeFracMKNFp16;
  83. rtCubeFracMKNInt8_t cubeFracMKNInt8;
  84. rtVecFracVmulMKNFp16_t vecFracVmulMKNFp16;
  85. rtVecFracVmulMKNInt8_t vecFracVmulMKNInt8;
  86. } rtAiCoreSpec_t;
  87. typedef struct tagRtAiCoreRatesPara {
  88. uint32_t ddrRate;
  89. uint32_t l2Rate;
  90. uint32_t l2ReadRate;
  91. uint32_t l2WriteRate;
  92. uint32_t l1ToL0ARate;
  93. uint32_t l1ToL0BRate;
  94. uint32_t l0CToUBRate;
  95. uint32_t ubToL2;
  96. uint32_t ubToDDR;
  97. uint32_t ubToL1;
  98. } rtAiCoreMemoryRates_t;
  99. typedef struct tagRtMemoryConfig {
  100. uint32_t flowtableSize;
  101. uint32_t compilerSize;
  102. } rtMemoryConfig_t;
  103. typedef struct tagRtPlatformConfig { uint32_t platformConfig; } rtPlatformConfig_t;
  104. /**
  105. * @ingroup
  106. * @brief get AI core count
  107. * @param [in] aiCoreCnt
  108. * @return aiCoreCnt
  109. */
  110. RTS_API rtError_t rtGetAiCoreCount(uint32_t *aiCoreCnt);
  111. /**
  112. * @ingroup
  113. * @brief get AI cpu count
  114. * @param [in] aiCpuCnt
  115. * @return aiCpuCnt
  116. */
  117. RTS_API rtError_t rtGetAiCpuCount(uint32_t *aiCpuCnt);
  118. /**
  119. * @ingroup
  120. * @brief get AI core frequency
  121. * @param [in] aiCoreSpec
  122. * @return aiCoreSpec
  123. */
  124. RTS_API rtError_t rtGetAiCoreSpec(rtAiCoreSpec_t *aiCoreSpec);
  125. /**
  126. * @ingroup
  127. * @brief AI get core band Info
  128. * @param [in] aiCoreMemoryRates
  129. * @return aiCoreMemoryRates
  130. */
  131. RTS_API rtError_t rtGetAiCoreMemoryRates(rtAiCoreMemoryRates_t *aiCoreMemoryRates);
  132. /**
  133. * @ingroup
  134. * @brief AI get core buffer Info,FlowTable Size,Compiler Size
  135. * @param [in] memoryConfig
  136. * @return memoryConfig
  137. */
  138. RTS_API rtError_t rtGetMemoryConfig(rtMemoryConfig_t *memoryConfig);
  139. /**
  140. * @ingroup
  141. * @brief get l2 buffer Info,virtual baseaddr,Size
  142. * @param [in] stream
  143. * @return RT_ERROR_NONE for ok, errno for failed
  144. */
  145. RTS_API rtError_t rtMemGetL2Info(rtStream_t stream, void **ptr, uint32_t *size);
  146. /**
  147. * @ingroup
  148. * @brief get runtime version. The version is returned as (1000 major + 10 minor). For example, RUNTIME 9.2 would be represented by 9020.
  149. * @param [out] runtimeVersion
  150. * @return RT_ERROR_NONE for ok
  151. * @return RT_ERROR_INVALID_VALUE for error input
  152. */
  153. RTS_API rtError_t rtGetRuntimeVersion(uint32_t *runtimeVersion);
  154. #if defined(__cplusplus) && !defined(COMPILE_OMG_PACKAGE)
  155. }
  156. #endif
  157. #endif // __CCE_RUNTIME_STREAM_H__

图引擎模块(GE)是MindSpore的一个子模块,其代码由C++实现,位于前端模块ME和底层硬件之间,起到承接作用。图引擎模块以ME下发的图作为输入,然后进行一系列的深度图优化操作,最后输出一张可以在底层硬件上高效运行的图。GE针对昇腾AI处理器的硬件结构特点,做了特定的优化工作,以此来充分发挥出昇腾AI处理器的强大算力。在进行模型训练/推理时,GE会被自动调用而用户并不感知。GE主要由GE API和GE Core两部分组成,详细的架构图如下所示