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config.h 6.5 kB

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  1. /**
  2. * Copyright 2020 Huawei Technologies Co., Ltd
  3. * Licensed under the Apache License, Version 2.0 (the "License");
  4. * you may not use this file except in compliance with the License.
  5. * You may obtain a copy of the License at
  6. * http://www.apache.org/licenses/LICENSE-2.0
  7. * Unless required by applicable law or agreed to in writing, software
  8. * distributed under the License is distributed on an "AS IS" BASIS,
  9. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. * See the License for the specific language governing permissions and
  11. * limitations under the License.
  12. */
  13. #ifndef CCE_RUNTIME_CONFIG_H
  14. #define CCE_RUNTIME_CONFIG_H
  15. #include "base.h"
  16. #if defined(__cplusplus)
  17. extern "C" {
  18. #endif
  19. #define PLAT_COMBINE(arch, chip, ver) (((arch) << 16U) | ((chip) << 8U) | (ver))
  20. #define PLAT_GET_ARCH(type) (((type) >> 16U) & 0xffffU)
  21. #define PLAT_GET_CHIP(type) (((type) >> 8U) & 0xffU)
  22. #define PLAT_GET_VER(type) ((type) & 0xffU)
  23. typedef enum tagRtArchType {
  24. ARCH_BEGIN = 0,
  25. ARCH_V100 = ARCH_BEGIN,
  26. ARCH_V200 = 1,
  27. ARCH_END = 2,
  28. } rtArchType_t;
  29. typedef enum tagRtChipType {
  30. CHIP_BEGIN = 0,
  31. CHIP_MINI = CHIP_BEGIN,
  32. CHIP_CLOUD = 1,
  33. CHIP_MDC = 2,
  34. CHIP_LHISI = 3,
  35. CHIP_DC = 4,
  36. CHIP_CLOUD_V2 = 5,
  37. CHIP_NO_DEVICE = 6,
  38. CHIP_END = 7,
  39. } rtChipType_t;
  40. typedef enum tagRtAicpuScheType {
  41. SCHEDULE_SOFTWARE = 0, /* Software Schedule */
  42. SCHEDULE_SOFTWARE_OPT,
  43. SCHEDULE_HARDWARE, /* HWTS Schedule */
  44. } rtAicpuScheType;
  45. typedef enum tagRtDeviceCapabilityType {
  46. RT_SCHEDULE_SOFTWARE = 0, // Software Schedule
  47. RT_SCHEDULE_SOFTWARE_OPT,
  48. RT_SCHEDULE_HARDWARE, // HWTS Schedule
  49. RT_AICPU_BLOCKING_OP_NOT_SUPPORT,
  50. RT_AICPU_BLOCKING_OP_SUPPORT, // 1910/1980/1951 ts support AICPU blocking operation
  51. RT_MODE_NO_FFTS, // no ffts
  52. RT_MODE_FFTS, // 1981 get ffts work mode, ffts
  53. RT_MODE_FFTS_PLUS, // 1981 get ffts work mode, ffts plus
  54. } rtDeviceCapabilityType;
  55. typedef enum tagRtVersion {
  56. VER_BEGIN = 0,
  57. VER_NA = VER_BEGIN,
  58. VER_ES = 1,
  59. VER_CS = 2,
  60. VER_SD3403 = 3,
  61. VER_END = 4,
  62. } rtVersion_t;
  63. /* match rtChipType_t */
  64. typedef enum tagRtPlatformType {
  65. PLATFORM_BEGIN = 0,
  66. PLATFORM_MINI_V1 = PLATFORM_BEGIN,
  67. PLATFORM_CLOUD_V1 = 1,
  68. PLATFORM_MINI_V2 = 2,
  69. PLATFORM_LHISI_ES = 3,
  70. PLATFORM_LHISI_CS = 4,
  71. PLATFORM_DC = 5,
  72. PLATFORM_CLOUD_V2 = 6,
  73. PLATFORM_LHISI_SD3403 = 7,
  74. PLATFORM_END = 8,
  75. } rtPlatformType_t;
  76. typedef enum tagRtCubeFracMKNFp16 {
  77. RT_CUBE_MKN_FP16_2_16_16 = 0,
  78. RT_CUBE_MKN_FP16_4_16_16,
  79. RT_CUBE_MKN_FP16_16_16_16,
  80. RT_CUBE_MKN_FP16_Default,
  81. } rtCubeFracMKNFp16_t;
  82. typedef enum tagRtCubeFracMKNInt8 {
  83. RT_CUBE_MKN_INT8_2_32_16 = 0,
  84. RT_CUBE_MKN_INT8_4_32_4,
  85. RT_CUBE_MKN_INT8_4_32_16,
  86. RT_CUBE_MKN_INT8_16_32_16,
  87. RT_CUBE_MKN_INT8_Default,
  88. } rtCubeFracMKNInt8_t;
  89. typedef enum tagRtVecFracVmulMKNFp16 {
  90. RT_VEC_VMUL_MKN_FP16_1_16_16 = 0,
  91. RT_VEC_VMUL_MKN_FP16_Default,
  92. } rtVecFracVmulMKNFp16_t;
  93. typedef enum tagRtVecFracVmulMKNInt8 {
  94. RT_VEC_VMUL_MKN_INT8_1_32_16 = 0,
  95. RT_VEC_VMUL_MKN_INT8_Default,
  96. } rtVecFracVmulMKNInt8_t;
  97. typedef struct tagRtAiCoreSpec {
  98. uint32_t cubeFreq;
  99. uint32_t cubeMSize;
  100. uint32_t cubeKSize;
  101. uint32_t cubeNSize;
  102. rtCubeFracMKNFp16_t cubeFracMKNFp16;
  103. rtCubeFracMKNInt8_t cubeFracMKNInt8;
  104. rtVecFracVmulMKNFp16_t vecFracVmulMKNFp16;
  105. rtVecFracVmulMKNInt8_t vecFracVmulMKNInt8;
  106. } rtAiCoreSpec_t;
  107. typedef struct tagRtAiCoreRatesPara {
  108. uint32_t ddrRate;
  109. uint32_t l2Rate;
  110. uint32_t l2ReadRate;
  111. uint32_t l2WriteRate;
  112. uint32_t l1ToL0ARate;
  113. uint32_t l1ToL0BRate;
  114. uint32_t l0CToUBRate;
  115. uint32_t ubToL2;
  116. uint32_t ubToDDR;
  117. uint32_t ubToL1;
  118. } rtAiCoreMemoryRates_t;
  119. typedef struct tagRtMemoryConfig {
  120. uint32_t flowtableSize;
  121. uint32_t compilerSize;
  122. } rtMemoryConfig_t;
  123. typedef struct tagRtPlatformConfig {
  124. uint32_t platformConfig;
  125. } rtPlatformConfig_t;
  126. typedef enum tagRTTaskTimeoutType {
  127. RT_TIMEOUT_TYPE_OP_WAIT = 0,
  128. RT_TIMEOUT_TYPE_OP_EXECUTE,
  129. } rtTaskTimeoutType_t;
  130. /**
  131. * @ingroup
  132. * @brief get AI core count
  133. * @param [in] aiCoreCnt
  134. * @return aiCoreCnt
  135. */
  136. RTS_API rtError_t rtGetAiCoreCount(uint32_t *aiCoreCnt);
  137. /**
  138. * @ingroup
  139. * @brief get AI cpu count
  140. * @param [in] aiCpuCnt
  141. * @return aiCpuCnt
  142. */
  143. RTS_API rtError_t rtGetAiCpuCount(uint32_t *aiCpuCnt);
  144. /**
  145. * @ingroup
  146. * @brief get AI core frequency
  147. * @param [in] aiCoreSpec
  148. * @return aiCoreSpec
  149. */
  150. RTS_API rtError_t rtGetAiCoreSpec(rtAiCoreSpec_t *aiCoreSpec);
  151. /**
  152. * @ingroup
  153. * @brief AI get core band Info
  154. * @param [in] aiCoreMemoryRates
  155. * @return aiCoreMemoryRates
  156. */
  157. RTS_API rtError_t rtGetAiCoreMemoryRates(rtAiCoreMemoryRates_t *aiCoreMemoryRates);
  158. /**
  159. * @ingroup
  160. * @brief AI get core buffer Info,FlowTable Size,Compiler Size
  161. * @param [in] memoryConfig
  162. * @return memoryConfig
  163. */
  164. RTS_API rtError_t rtGetMemoryConfig(rtMemoryConfig_t *memoryConfig);
  165. /**
  166. * @ingroup
  167. * @brief get l2 buffer Info,virtual baseaddr,Size
  168. * @param [in] stream
  169. * @return RT_ERROR_NONE for ok, errno for failed
  170. */
  171. RTS_API rtError_t rtMemGetL2Info(rtStream_t stream, void **ptr, uint32_t *size);
  172. /**
  173. * @ingroup
  174. * @brief get runtime version. The version is returned as (1000 major + 10 minor). For example, RUNTIME 9.2 would be
  175. * represented by 9020.
  176. * @param [out] runtimeVersion
  177. * @return RT_ERROR_NONE for ok
  178. * @return RT_ERROR_INVALID_VALUE for error input
  179. */
  180. RTS_API rtError_t rtGetRuntimeVersion(uint32_t *runtimeVersion);
  181. /**
  182. * @ingroup
  183. * @brief get device feature ability by device id, such as task schedule ability.
  184. * @param [in] deviceId
  185. * @param [in] moduleType
  186. * @param [in] featureType
  187. * @param [out] value
  188. * @return RT_ERROR_NONE for ok
  189. * @return RT_ERROR_INVALID_VALUE for error input
  190. */
  191. RTS_API rtError_t rtGetDeviceCapability(int32_t deviceId, int32_t moduleType, int32_t featureType, int32_t *value);
  192. /**
  193. * @ingroup
  194. * @brief set event wait task timeout time.
  195. * @param [in] timeout
  196. * @return RT_ERROR_NONE for ok
  197. * @return RT_ERROR_INVALID_VALUE for error input
  198. */
  199. RTS_API rtError_t rtSetOpWaitTimeOut(uint32_t timeout);
  200. /**
  201. * @ingroup
  202. * @brief set op execute task timeout time.
  203. * @param [in] timeout
  204. * @return RT_ERROR_NONE for ok
  205. * @return RT_ERROR_INVALID_VALUE for error input
  206. */
  207. RTS_API rtError_t rtSetOpExecuteTimeOut(uint32_t timeout);
  208. #if defined(__cplusplus)
  209. }
  210. #endif
  211. #endif // CCE_RUNTIME_CONFIG_H

图引擎模块(GE)是MindSpore的一个子模块,其代码由C++实现,位于前端模块ME和底层硬件之间,起到承接作用。图引擎模块以ME下发的图作为输入,然后进行一系列的深度图优化操作,最后输出一张可以在底层硬件上高效运行的图。GE针对昇腾AI处理器的硬件结构特点,做了特定的优化工作,以此来充分发挥出昇腾AI处理器的强大算力。在进行模型训练/推理时,GE会被自动调用而用户并不感知。GE主要由GE API和GE Core两部分组成,详细的架构图如下所示