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config.h 6.9 kB

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  1. /**
  2. * Copyright 2019-2020 Huawei Technologies Co., Ltd
  3. *
  4. * Licensed under the Apache License, Version 2.0 (the "License");
  5. * you may not use this file except in compliance with the License.
  6. * You may obtain a copy of the License at
  7. *
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. *
  10. * Unless required by applicable law or agreed to in writing, software
  11. * distributed under the License is distributed on an "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13. * See the License for the specific language governing permissions and
  14. * limitations under the License.
  15. */
  16. #ifndef CCE_RUNTIME_CONFIG_H
  17. #define CCE_RUNTIME_CONFIG_H
  18. #include "base.h"
  19. #if defined(__cplusplus)
  20. extern "C" {
  21. #endif
  22. #define PLAT_COMBINE(arch, chip, ver) (((arch) << 16U) | ((chip) << 8U) | (ver))
  23. #define PLAT_GET_ARCH(type) (((type) >> 16U) & 0xffffU)
  24. #define PLAT_GET_CHIP(type) (((type) >> 8U) & 0xffU)
  25. #define PLAT_GET_VER(type) ((type) & 0xffU)
  26. typedef enum tagRtArchType {
  27. ARCH_BEGIN = 0,
  28. ARCH_V100 = ARCH_BEGIN,
  29. ARCH_V200 = 1,
  30. ARCH_END = 2,
  31. } rtArchType_t;
  32. typedef enum tagRtChipType {
  33. CHIP_BEGIN = 0,
  34. CHIP_MINI = CHIP_BEGIN,
  35. CHIP_CLOUD = 1,
  36. CHIP_MDC = 2,
  37. CHIP_LHISI = 3,
  38. CHIP_DC = 4,
  39. CHIP_CLOUD_V2 = 5,
  40. CHIP_NO_DEVICE = 6,
  41. CHIP_END = 7,
  42. } rtChipType_t;
  43. typedef enum tagRtAicpuScheType {
  44. SCHEDULE_SOFTWARE = 0, /* Software Schedule */
  45. SCHEDULE_SOFTWARE_OPT,
  46. SCHEDULE_HARDWARE, /* HWTS Schedule */
  47. } rtAicpuScheType;
  48. typedef enum tagRtDeviceCapabilityType {
  49. RT_SCHEDULE_SOFTWARE = 0, // Software Schedule
  50. RT_SCHEDULE_SOFTWARE_OPT,
  51. RT_SCHEDULE_HARDWARE, // HWTS Schedule
  52. RT_AICPU_BLOCKING_OP_NOT_SUPPORT,
  53. RT_AICPU_BLOCKING_OP_SUPPORT, // 1910/1980/1951 ts support AICPU blocking operation
  54. RT_MODE_NO_FFTS, // no ffts
  55. RT_MODE_FFTS, // 1981 get ffts work mode, ffts
  56. RT_MODE_FFTS_PLUS, // 1981 get ffts work mode, ffts plus
  57. } rtDeviceCapabilityType;
  58. typedef enum tagRtVersion {
  59. VER_BEGIN = 0,
  60. VER_NA = VER_BEGIN,
  61. VER_ES = 1,
  62. VER_CS = 2,
  63. VER_SD3403 = 3,
  64. VER_END = 4,
  65. } rtVersion_t;
  66. /* match rtChipType_t */
  67. typedef enum tagRtPlatformType {
  68. PLATFORM_BEGIN = 0,
  69. PLATFORM_MINI_V1 = PLATFORM_BEGIN,
  70. PLATFORM_CLOUD_V1 = 1,
  71. PLATFORM_MINI_V2 = 2,
  72. PLATFORM_LHISI_ES = 3,
  73. PLATFORM_LHISI_CS = 4,
  74. PLATFORM_DC = 5,
  75. PLATFORM_CLOUD_V2 = 6,
  76. PLATFORM_LHISI_SD3403 = 7,
  77. PLATFORM_END = 8,
  78. } rtPlatformType_t;
  79. typedef enum tagRtCubeFracMKNFp16 {
  80. RT_CUBE_MKN_FP16_2_16_16 = 0,
  81. RT_CUBE_MKN_FP16_4_16_16,
  82. RT_CUBE_MKN_FP16_16_16_16,
  83. RT_CUBE_MKN_FP16_Default,
  84. } rtCubeFracMKNFp16_t;
  85. typedef enum tagRtCubeFracMKNInt8 {
  86. RT_CUBE_MKN_INT8_2_32_16 = 0,
  87. RT_CUBE_MKN_INT8_4_32_4,
  88. RT_CUBE_MKN_INT8_4_32_16,
  89. RT_CUBE_MKN_INT8_16_32_16,
  90. RT_CUBE_MKN_INT8_Default,
  91. } rtCubeFracMKNInt8_t;
  92. typedef enum tagRtVecFracVmulMKNFp16 {
  93. RT_VEC_VMUL_MKN_FP16_1_16_16 = 0,
  94. RT_VEC_VMUL_MKN_FP16_Default,
  95. } rtVecFracVmulMKNFp16_t;
  96. typedef enum tagRtVecFracVmulMKNInt8 {
  97. RT_VEC_VMUL_MKN_INT8_1_32_16 = 0,
  98. RT_VEC_VMUL_MKN_INT8_Default,
  99. } rtVecFracVmulMKNInt8_t;
  100. typedef struct tagRtAiCoreSpec {
  101. uint32_t cubeFreq;
  102. uint32_t cubeMSize;
  103. uint32_t cubeKSize;
  104. uint32_t cubeNSize;
  105. rtCubeFracMKNFp16_t cubeFracMKNFp16;
  106. rtCubeFracMKNInt8_t cubeFracMKNInt8;
  107. rtVecFracVmulMKNFp16_t vecFracVmulMKNFp16;
  108. rtVecFracVmulMKNInt8_t vecFracVmulMKNInt8;
  109. } rtAiCoreSpec_t;
  110. typedef struct tagRtAiCoreRatesPara {
  111. uint32_t ddrRate;
  112. uint32_t l2Rate;
  113. uint32_t l2ReadRate;
  114. uint32_t l2WriteRate;
  115. uint32_t l1ToL0ARate;
  116. uint32_t l1ToL0BRate;
  117. uint32_t l0CToUBRate;
  118. uint32_t ubToL2;
  119. uint32_t ubToDDR;
  120. uint32_t ubToL1;
  121. } rtAiCoreMemoryRates_t;
  122. typedef struct tagRtMemoryConfig {
  123. uint32_t flowtableSize;
  124. uint32_t compilerSize;
  125. } rtMemoryConfig_t;
  126. typedef struct tagRtPlatformConfig {
  127. uint32_t platformConfig;
  128. } rtPlatformConfig_t;
  129. typedef enum tagRTTaskTimeoutType {
  130. RT_TIMEOUT_TYPE_OP_WAIT = 0,
  131. RT_TIMEOUT_TYPE_OP_EXECUTE,
  132. } rtTaskTimeoutType_t;
  133. /**
  134. * @ingroup
  135. * @brief get AI core count
  136. * @param [in] aiCoreCnt
  137. * @return aiCoreCnt
  138. */
  139. RTS_API rtError_t rtGetAiCoreCount(uint32_t *aiCoreCnt);
  140. /**
  141. * @ingroup
  142. * @brief get AI cpu count
  143. * @param [in] aiCpuCnt
  144. * @return aiCpuCnt
  145. */
  146. RTS_API rtError_t rtGetAiCpuCount(uint32_t *aiCpuCnt);
  147. /**
  148. * @ingroup
  149. * @brief get AI core frequency
  150. * @param [in] aiCoreSpec
  151. * @return aiCoreSpec
  152. */
  153. RTS_API rtError_t rtGetAiCoreSpec(rtAiCoreSpec_t *aiCoreSpec);
  154. /**
  155. * @ingroup
  156. * @brief AI get core band Info
  157. * @param [in] aiCoreMemoryRates
  158. * @return aiCoreMemoryRates
  159. */
  160. RTS_API rtError_t rtGetAiCoreMemoryRates(rtAiCoreMemoryRates_t *aiCoreMemoryRates);
  161. /**
  162. * @ingroup
  163. * @brief AI get core buffer Info,FlowTable Size,Compiler Size
  164. * @param [in] memoryConfig
  165. * @return memoryConfig
  166. */
  167. RTS_API rtError_t rtGetMemoryConfig(rtMemoryConfig_t *memoryConfig);
  168. /**
  169. * @ingroup
  170. * @brief get l2 buffer Info,virtual baseaddr,Size
  171. * @param [in] stream
  172. * @return RT_ERROR_NONE for ok, errno for failed
  173. */
  174. RTS_API rtError_t rtMemGetL2Info(rtStream_t stream, void **ptr, uint32_t *size);
  175. /**
  176. * @ingroup
  177. * @brief get runtime version. The version is returned as (1000 major + 10 minor). For example, RUNTIME 9.2 would be
  178. * represented by 9020.
  179. * @param [out] runtimeVersion
  180. * @return RT_ERROR_NONE for ok
  181. * @return RT_ERROR_INVALID_VALUE for error input
  182. */
  183. RTS_API rtError_t rtGetRuntimeVersion(uint32_t *runtimeVersion);
  184. /**
  185. * @ingroup
  186. * @brief get device feature ability by device id, such as task schedule ability.
  187. * @param [in] deviceId
  188. * @param [in] moduleType
  189. * @param [in] featureType
  190. * @param [out] value
  191. * @return RT_ERROR_NONE for ok
  192. * @return RT_ERROR_INVALID_VALUE for error input
  193. */
  194. RTS_API rtError_t rtGetDeviceCapability(int32_t deviceId, int32_t moduleType, int32_t featureType, int32_t *value);
  195. /**
  196. * @ingroup
  197. * @brief set event wait task timeout time.
  198. * @param [in] timeout
  199. * @return RT_ERROR_NONE for ok
  200. * @return RT_ERROR_INVALID_VALUE for error input
  201. */
  202. RTS_API rtError_t rtSetOpWaitTimeOut(uint32_t timeout);
  203. /**
  204. * @ingroup
  205. * @brief set op execute task timeout time.
  206. * @param [in] timeout
  207. * @return RT_ERROR_NONE for ok
  208. * @return RT_ERROR_INVALID_VALUE for error input
  209. */
  210. RTS_API rtError_t rtSetOpExecuteTimeOut(uint32_t timeout);
  211. /**
  212. * @ingroup
  213. * @brief get is Heterogenous.
  214. * @param [out] heterogenous=1 Heterogenous Mode: read isHeterogenous=1 in ini file.
  215. * @param [out] heterogenous=0 NOT Heterogenous Mode:
  216. * 1:not found ini file, 2:error when reading ini, 3:Heterogenous value is not 1
  217. * @return RT_ERROR_NONE for ok
  218. */
  219. RTS_API rtError_t rtGetIsHeterogenous(int32_t *heterogenous);
  220. #if defined(__cplusplus)
  221. }
  222. #endif
  223. #endif // CCE_RUNTIME_CONFIG_H

图引擎模块(GE)是MindSpore的一个子模块,其代码由C++实现,位于前端模块ME和底层硬件之间,起到承接作用。图引擎模块以ME下发的图作为输入,然后进行一系列的深度图优化操作,最后输出一张可以在底层硬件上高效运行的图。GE针对昇腾AI处理器的硬件结构特点,做了特定的优化工作,以此来充分发挥出昇腾AI处理器的强大算力。在进行模型训练/推理时,GE会被自动调用而用户并不感知。GE主要由GE API和GE Core两部分组成,详细的架构图如下所示